Senior Full Chip Layout Engineer

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What You'll Be Doing

• Perform physical layout for full-chip level, integration, pinning and bump route
• Work with block owners and project managers to assure high quality convergence in all layout aspects
• You will be responsible for chip layout from the floorplanning stage through tape-out
  
  

• An Electronics Engineer certificate or a B.Sc. in Electrical Engineering
• You should have 5 years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.
• A strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes, is required
• Knowledge in scripts' language: TCL, Unix and Shell
• Experience in Linux environments
• AI tools orientation or alternatively a desire to learn
• Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus)
• Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)
• Self-motivation, attention to detail and good interpersonal skills
  
  

• Experience in methodology definition / flow owner of Full-chip / Place and Route
• Great teammate
• Ownership, self-learning skills and ability to work autonomously