Physical Design Engineer

A highly successful, established Israeli semiconductor corporation pioneering advanced connectivity chipsets and high-speed communications hardware for the global automotive and professional audio-video (Pro AV) markets.

The company has engineered a disruptive, proprietary transmission technology that enables the ultra-fast, high-fidelity transfer of uncompressed data streams over simple, thin cabling across extended distances.

Housing several hundred elite professionals, the corporation drives end-to-end silicon innovation, scaling its multi-disciplinary architectures into high-volume global markets.

The company's primary R&D facility is located in the Central region of Israel, operating under a flexible hybrid structure that supports integrated remote work flexibility.

Position Overview-

• Senior Physical Design / VLSI Backend Engineer joining a core digital design group to own the full physical implementation lifecycle of complex SoC blocks from Netlist to GDSII.
• Executing the complete Place & Route (P&R) flow across both hierarchical and top-level block design stages to ensure optimized silicon layouts.
• Managing critical layout engineering metrics, including cell placement, high-performance clock tree synthesis (CTS), advanced routing, Static Timing Analysis (STA), and complete physical verification (DRC, LVS, Antenna).
• Driving strict timing closure and design convergence across multiple implementation phases while proactively mitigating physical constraints like IR drop and electromigration (EM).
• Collaborating cross-functionally with Frontend Design, Architecture, and Verification teams to deliver high-quality, sign-off ready silicon.
• Core Domain & Ecosystem- VLSI Backend Design, Netlist-to-GDSII, Automatic Place & Route (P&R), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification (DRC/LVS/ANT), Circuit Optimization, TCL Scripting, Cadence Innovus / Digital Design Flows, and Advanced Technology Nodes (16nm/7nm/5nm).

Requirements-

• Academic Background: B.Sc. in Electrical Engineering, Electronic Engineering, or an equivalent exact science discipline from a recognized academic institution – Mandatory
• 6+ years of proven professional experience executing automatic Place & Route (P&R) flows across both block-level and top-level designs – Mandatory
• Strong technical automation skills with hands-on proficiency writing custom deployment scripts in TCL – Mandatory
• Robust engineering comprehension of circuit optimization, IR drop mitigation, and Electromigration (EM) prevention considerations – Significant Advantage
• Production-proven experience operating with Cadence physical design tools and backend flows (e.g., Innovus) – Significant Advantage
• Direct, practical knowledge working on advanced sub-micron technology nodes (16nm and below) – Significant Advantage
• Excellent problem-solving skills, an analytical mindset, and a strong capacity for multidisciplinary team collaboration – Mandatory