Verification Engineer

A premier, well-established global Semiconductor leader specializing in the design and manufacturing of ultra-low-power SoCs and silicon solutions for IoT, cellular connectivity, edge AI, camera sensors, and hardware security.

The company's innovative chips power millions of consumer and industrial devices worldwide, from tier-1 smart wearables and automotive systems to connected cameras and enterprise tracking solutions.

Employing hundreds of top-tier silicon and software engineers, the company combines deep domain expertise and market stability with cutting-edge chip architectures.

Located in the Sharon region, operating on a hybrid work model with 1 day WFH per week.

Role Description0

• Serving as a Senior SoC Verification Engineer, joining an established silicon verification squad reporting directly to the Verification Team Lead.
• Leading end-to-end verification strategies and methodologies for complex, next-generation SoC / ASIC architectures.
• Defining comprehensive verification test plans, architecting advanced, reusable verification environments and components using SystemVerilog / Specman (UVM / eRM).
• Driving complete verification cycles through testbench implementation, constrained-random testing, and achieving 100% Coverage Closure (code, functional, and assertion-based).
• Leading deep-dive debugging of complex integration bugs, working closely with Chip Design (RTL), System Architecture, and Embedded Software teams.
• Developing reusable verification IP (VIP) and optimizing simulation performance and automation workflows.

Requirements-

• B.Sc. in Electrical Engineering, Electronics Engineering, or a related discipline from an accredited university – Mandatory
• 5+ years of hands-on experience as a SoC / ASIC Verification Engineer – Mandatory
• Proven track record from within the Semiconductor / Fabless industry – Mandatory
• Deep, proven expertise in advanced verification methodologies: SystemVerilog (UVM) or Specman (e / eRM) – Mandatory
• Extensive hands-on experience in building Testbenches from scratch, Coverage Closure, and Assertions (SVA) – Mandatory
• Strong technical debugging skills across RTL, gate-level simulations, and hardware-software integration layers – Mandatory
• Familiarity with standard bus protocols and interfaces (e.g., AXI, AHB, APB, PCIe, USB, MIPI, I2C/SPI) – Significant Advantage