Package Substrate Layout Engineer

Description

The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.

The team collaborates with the Backend team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin-out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on Package substrate layout and high speed PCB layout.

We are seeking an experienced PCB Layout Engineer to join circuit board design and layout initiatives. This role requires a seasoned professional with deep expertise in complex PCB and substrate design, capable of driving design excellence.

Key job responsibilities

• Design and Layout of large and complex PCBs.
• Design and Layout of package substrates.
• Understanding package substrate technologies and layout design rules.
• Proficiency in Signal and Power Integrity considerations.
• Layout test studies of Die bump-out structures and Package substrate breakout.
• Layout test studies of Package pin-out arrangements and PCB board implementation.
• Continuously improve the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.
  
  

• Bachelor's degree in electrical engineering or equivalent
• 7+ years of professional PCB layout design experience
• Proven expertise in substrate layout design and high-density interconnect (HDI) technologies
• Advanced proficiency with industry-standard Cadence CAD
• Experience with PCB manufacturing processes and design for manufacturability (DFM)
  
  

• Strong background in PCB layout.
• Experience with advanced packaging technologies (BGA, flip-chip)
• Knowledge of controlled impedance design
• Familiarity with high-frequency/RF layout