Experienced ASIC / RTL Logic Design Engineer – Camera

We are looking for an experienced ASIC Front-End / RTL Logic Design Engineer to join a VLSI team developing advanced Camera and Image Processing technology.

This is not an entry-level position. At least 2 years of hands-on industry experience in Logic / RTL Design is required.

What you’ll do

- Define micro-architecture from specifications

- Develop and debug synthesizable RTL

- Own digital design blocks from definition through implementation

- Work closely with Architecture, Verification, Physical Design, SW and FW teams

- Work with digital design flows including simulation, synthesis, lint and timing analysis

What we’re looking for

- 2–5 years of professional experience in Logic / RTL Design

- Hands-on experience in ASIC Front-End

- Strong experience with micro-architecture definition and RTL development/debug

- Experience with Verilog / SystemVerilog

B.Sc. in Electrical Engineering, Computer Engineering or related field

Advantage

- Experience in Image Processing / ISP

- Pixel processing, filters or convolution

- Experience with scalable hardware design

- Familiarity with synthesis, lint, timing analysis and formal verification

- Understanding of HW interaction with SW/FW

Please note: academic RTL/VLSI projects alone are not sufficient for this position.