Verification Engineer

A global Deep-Tech leader in Quantum Computing, developing an enterprise-grade HW/SW control platform and operating system for quantum processors.

Currently deployed in production across premier research institutes, governments, and global tech enterprises, the platform bridges advanced hardware logic with complex software environments.

Backed by substantial multi-million dollar venture capital funding from top-tier international funds alongside strategic international acquisitions, the company employs approximately 350 professionals globally, maintaining its primary R&D hub in Israel.

Located in central Tel Aviv (walking distance from the train station), operating on a hybrid work model with 2 days WFH per week.

Role Description-

• Joining a specialized team of 5 Verification Engineers, driving Full-Chip and System-Level Verification within a multidisciplinary Hardware/Software ecosystem.
• Establishing complex verification environments from scratch, developing custom Drivers, Monitors, Scoreboards, and Coverage models.
• Authoring comprehensive Test Plans and defining end-to-end verification methodologies.
• Integrating and working with Verification IPs (VIPs) and industry protocols including PCIe, DDR, and AXI.
• Building complex verification sequences, integrating Reference Models, and collaborating closely with Hardware Design, Software Engineering, and Quantum Physics teams.

Requirements-

• 5+ years of hands-on experience in ASIC / System-Level Verification – Mandatory
• Proven capability to build and ramp up Verification Environments from scratch – Mandatory
• Solid knowledge of Verification IPs (VIPs) and protocols (PCIe, DDR, AXI) – Mandatory
• Hands-on experience with UVM and SystemVerilog methodologies – Advantage
• Deep understanding of Hardware / Software interactions and system-level architectures – Advantage
• Proficiency in programming/scripting languages: C, C++, Python, or SystemC – Advantage