Verification Engineer

A high-growth, innovative Semiconductor & IoT startup revolutionizing smart packaging and item-level connectivity.

The company develops self-powered IoT ambient-harvesting tags driven by RF energy, combining cloud platforms and advanced semiconductor architecture to bring digital intelligence to everyday products globally.

Demonstrating strong commercial momentum and financial stability, the company employs around 250 professionals across its primary R&D hub in Israel and global locations.

Located in the Northern (walking distance from the train station), operating on a hybrid work model with 1 day WFH per week.

Role Description-

• Joining as a Lead / Senior ASIC Design Verification Engineer, driving the full verification lifecycle and methodology for complex IoT Semiconductor solutions.
• Designing, building, and maintaining robust SV/UVM Block-level and Full-Chip environments.
• Defining comprehensive verification test plans, coverage metrics, and ensuring full verification closure across complex Mixed-Signal SoC architectures.
• Performing multi-domain verification utilizing Verilog, MATLAB, HW/SW Co-simulation, and hands-on lab integration.
• Collaborating closely with cross-functional R&D units including Digital RTL, Analog, Embedded Software, and Systems Engineering teams.

Requirements-

• B.Sc. in Electrical Engineering, Electronics Engineering, or a related discipline – Mandatory
• 5 years of hands-on experience in ASIC / SoC Design Verification – Mandatory
• Deep expertise and practical experience with SystemVerilog (SV) and UVM methodologies – Mandatory
• Solid background in RTL design concepts and digital ASIC development flows – Mandatory
• Proven track record in SoC / Full-Chip verification, simulation tools, and advanced debugging – Mandatory
• Experience working in Unix/Linux environments with scripting capabilities (Python, Perl, or Bash) – Mandatory
• Experience working with modern Version Control platforms (e.g., Git, Perforce) – Mandatory
• Knowledge of Low Power Verification and UPF standards – Advantage
• Experience in Mixed-Signal SoC verification – Advantage
• Background in HW/SW Co-development and Co-simulation methodologies – Advantage