עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
A premier Israeli-American Semiconductor and Deep-Tech startup specializing in Optical Communication and AI Infrastructure solutions.
The company designs programmable, ultra-fast Coherent DSP Silicon to power high-speed, power-efficient data transfers across Data Centers, AI clusters, servers, and GPUs.
Well-funded by premier venture capital firms, the company maintains high financial stability and operates globally with around 110 employees, with its core R&D hub located in Israel.
Located in the Bursa district, Ramat Gan (walking distance from the central train station), operating on a hybrid work model with 2 days WFH / 3 days in-office per week.
Role Description-
- Joining the VLSI group as a Digital ASIC/FPGA Design Engineer, taking part in end-to-end hardware development for advanced coherent communication chips from concept and initial architecture to silicon.
- Defining Digital Block architectures, specifying system interfaces, data paths, and high-performance throughput requirements.
- Implementing complex Logic Design using Verilog / SystemVerilog (RTL).
- Collaborating closely with cross-functional R&D squads including Architecture, Verification, DSP/Algorithms, Analog, and System engineering teams.
- Participating in static timing analysis (STA), synthesis checks, and verification simulation environments to ensure first-time-right silicon execution.
Requirements-
- B.Sc. in Electrical Engineering, Computer Engineering, or a related scientific discipline from a recognized University – Mandatory
- Proven hands-on experience as a Digital ASIC / FPGA Designer – Mandatory
- Significant expertise in RTL coding using Verilog and SystemVerilog – Mandatory
- Hands-on experience in end-to-end Digital Design implementation – Mandatory
- Familiarity with Simulation Environments and Verification methodologies (e.g., UVM / SystemVerilog Verification) – Mandatory
- Understanding of high-speed digital architectures, SerDes, DSP blocks, or networking protocols – Advantage
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
ערב