Physical Design Engineer, Sr Staff

Description

What You'll Do

• Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
• Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
• Lead critical timing closure efforts — MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
• Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
• Architect and lead the development of scalable PD flow infrastructure using Python and TCL — including automated regression, sign-off reporting, and run management systems
• Champion the adoption of Agentic AI in the design flow — define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
• Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
• Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
• Mentor and technically guide junior and mid-level PD engineers across the organization

What You'll Need

• 10+ years of experience in digital Physical Design with a proven track record of tapeouts on FinFET nodes (N7 and below)
• Deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off
• Expert proficiency in EDA tools: Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk / Voltus, StarRC / Quantus
• Advanced Python and TCL scripting — ability to architect large-scale PD automation frameworks and flow infrastructure
• Proven experience in flow development: designing, implementing, and owning end-to-end backend design flows at team or organization level
• Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges — autonomous agents, AI-driven optimization, LLM-assisted debugging
• Strong communication skills — ability to present methodology decisions, risk assessments, and tapeout readiness to senior management
• Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)

Preferred Experience

• Experience with chiplets, 2.5D/3D IC physical design, or advanced packaging technologies
• Familiarity with AI/ML-driven EDA tool evaluation and vendor collaboration
• Prior experience in a tech lead or staff engineering leadership role