Physical Design Engineer

A groundbreaking Deep-Tech startup operating in the High-Performance Computing (HPC) space, designing next-generation adaptive compute architectures for supercomputers and advanced data centers.

The company's proprietary technology drastically accelerates highly complex compute workloads across AI, Aerospace, Biotech, Energy, and Defense applications.

Founded by seasoned entrepreneurs and backed by top-tier venture capital, the company employs over 300 top-tier engineers globally.

Located in Tel Aviv, operating on a hybrid work model with 2 days WFH per week.

Role Description-

• Joining as a Physical Design / Backend Engineer leading end-to-end Physical Design activities for advanced high-performance ASIC components.
• Driving full-chip and block-level floorplanning, Power Grid design, Clock Tree Synthesis (CTS), and Place & Route (P&R) execution.
• Performing Static Timing Analysis (STA), constraint definitions, signal integrity optimizations, and timing closure under aggressive power and area targets.
• Owning physical verification flows including DRC, LVS, and ERC debugging.
• Collaborating closely with RTL, Synthesis, Architecture, and DFT teams to ensure seamless tape-out execution.

Requirements

• 3+ years of hands-on experience as a Physical Design Engineer / Backend Engineer – Mandatory
• Hands-on experience with Full-Chip and Block-level Floorplanning and Place & Route (P&R) – Mandatory
• Deep technical knowledge of Static Timing Analysis (STA), constraint definition, and timing closure – Mandatory
• Experience with Clock Tree Synthesis (CTS) and physically-aware synthesis methodologies – Mandatory
• Practical proficiency in Physical Verification debugging (DRC / LVS / ERC) – Mandatory
• B.Sc. in Electrical Engineering, Computer Engineering, or a related technical discipline – Advantage