FPGA Verification Engineer 241376

A leading aerospace and missile systems organization is seeking an experienced FPGA Verification Engineer to join a cutting-edge development team working on advanced programmable logic components for mission-critical systems.

Responsibilities

• Develop and execute Random-Based Verification environments for FPGA designs.
• Design and implement verification environments using SystemVerilog UVM methodology, from Test Plan definition through Random Constraints development and Functional Coverage implementation.
• Maintain and enhance existing (legacy) verification environments written in Verilog, VHDL, and SystemVerilog.
• Develop automation scripts in Python and TCL.
• Integrate and optimize verification environments for complex FPGA projects.
• Analyze verification results and provide comprehensive coverage reporting.

Requirements

• B.Sc. in Electrical & Electronics Engineering (Mandatory)
• At least 3 years of experience in FPGA/ASIC Verification
• Hands-on experience developing verification environments based on UVM and Reuse methodologies
• Experience integrating verification environments
• Experience implementing and reporting Functional Coverage
• Experience with UVM Scoreboard and UVM Register Model

Advantages

• Experience with Assertion-Based Verification (ABV)
• Strong familiarity with Verification IPs (VIPs) and their integration into verification environments
• Knowledge of communication protocols such as AXI, SPI, I2C, Ethernet (ETH), and PCIe
• Experience with FPGA design and development processes using VHDL/Verilog