Architectural Modeling Engineer

Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.

We’re looking for an experienced SW Engineer to join our Architectural Team, where you'll design and develop our hardware simulators that serve as the source of truth, drive architectural exploration and compiler optimization.

Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics. You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behavior.

Requirements

• BSc (or higher) in Computer Science, Math, Physics or Electrical Engineering.
• 5+ years of experience developing in modern C++ and Python
• Strong understanding of computer architecture and system-level modeling.
• Solid software engineering skills, including design, testing, performance tuning, and maintainability.
• Interest in SW-HW co-development environments, influencing both architecture and tooling.

Advantages

• Experience in SW-HW co-development environments.
• Experience in developing HW Simulators.
• Knowledge of SQL semantics and Parquet internals.

Responsibilities

• Develop new hardware simulators and continue evolving existing ones.
• Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
• Provide insights that influence chip architecture, compiler optimization, and system-level performance.
• Develop tools that drive the chip development cycle.