Principal Emulation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

• Emulation Flow Execution & Implementation
• Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
• Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
• Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
• System-Level Debug & Validation
• Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
• Ensure rapid cycles from RTL to functional stability through systematic debug approaches
• Own technical blocks and drive them to completion independently
• Cross-Functional Collaboration
• Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
• Ensure seamless hardware-software integration for AI infrastructure connectivity
• Collaborate with Design and Verification teams to optimize emulation strategies
  

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 10+ years of hands-on experience in Emulation at semiconductor companies
• Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)
• Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs
• Experience developing and maintaining execution flows for building, running, and debugging emulation models
• "Can-do" approach with ability to own technical blocks and drive them to completion independently
  
  

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis
• Proficiency in scripting languages such as Python or TCL for automation and flow enhancement
• Experience with standard debug environments (e.g., Verdi)
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)
• Background in hardware-software co-verification methodologies