עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- 4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
- Experience with industry-standard Automatic Test Pattern Generation (ATPG) methods, fault modeling, and scan coverage debug.
- Experience validating Memory Built-In Self-Test (MBIST) structures and Joint Test Action Group (JTAG)/ Test Access Port (TAP) controllers.
- Experience running structural verification, debugging testbenches, or simulation tracking utilizing simulators.
- Master's degree in Electrical Engineering.
- Experience with the Tessent shell environment, specifically extracting Instrument Connectivity Language (ICL) networks.
- Familiarity with Silicon bring-up and validation on Automatic Test Equipment (ATE) testers, including debugging hardware execution patterns.
- Proficiency using Python or Tcl to manage complex Electronic Design Automation (EDA) design and sign-off flows.
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
- Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
- Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
- Perform DFT verification at RTL and gate level.
- Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
שאלות ותשובות עבור משרת CPU Design for Test Engineer, Google Cloud
כמהנדס/ת CPU Design for Test ב-Google Cloud, תהיו אחראים/יות על תכנון, הטמעה ואימות של פתרונות Design for Testing (DFT) עבור מעגלים משולבים ספציפיים ליישום (ASICs). זה כולל פיתוח אסטרטגיית DFT למערכים, DFT היררכי, סריקה ו-ATPG, ביצוע ATPG וניפוי שגיאות בכיסוי סריקה, וכן עבודה עם צוותי הנדסה אחרים כדי להבטיח עמידה בדרישות ה-DFT.
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