VLSI Verification Engineer

A high-profile, venture-backed semiconductor stealth startup engineering a disruptive Artificial Intelligence technology paradigm designed specifically to accelerate chip design and compute architectures.

Co-founded by a renowned serial entrepreneur with a proven track record of elite scale-ups and high-valuation exits in the hardware and AI ecosystems, the enterprise is anchored by immense tier-1 funding.

The engineering roster comprises elite veterans hailing from the world’s leading fabless giants and cutting-edge deep-tech research hubs.

Located in Tel Aviv, the company operates under a hybrid structure that includes one day of remote work per week.

Position Overview-

• Senior ASIC / SoC Verification Engineer taking full technical ownership over the end-to-end (E2E) logic verification, stimulus architecture, and functional sign-off of highly intricate silicon systems.
• Architecting, building, and maintaining comprehensive, complex verification environments from scratch utilizing SystemVerilog and UVM methodologies.
• Defining verification plans, authoring constrained-random test cases, and extracting coverage metrics to ensure zero-defect convergence before tape-out.
• Collaborating side-by-side with Silicon Architects, RTL Design teams, and Validation squads to isolate, debug, and resolve systemic hardware-software design anomalies.
• Core Domain & Ecosystem- ASIC/SoC Functional Verification, SystemVerilog, Universal Verification Methodology (UVM), Constrained-Random Testing, RTL Analysis (Verilog/VHDL), Coverage-Driven Verification (CDV), Front-End Simulation Flows, and Industry-Standard EDA Suites (Synopsys, Cadence, Siemens/Mentor).

Requirements-

• Academic Background: B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or an equivalent exact science discipline from a recognized university – Mandatory
• 5 years of hands-on professional experience directly specializing in ASIC/SoC functional logic verification – Mandatory
• Production-proven mastery building testbenches and architectures using SystemVerilog, UVM, and constrained-random methodology constraints – Mandatory
• Strong structural understanding of digital logic design, RTL code review foundations (Verilog/VHDL), and advanced simulation pipelines – Mandatory
• Track record of deep-dive root-cause debugging across complex hardware/software system interactions – Mandatory
• Expert familiarity with tier-1 enterprise EDA toolsets (e.g., Cadence Xcelium, Synopsys VCS, or Siemens Questa) – Mandatory
• Excellent analytical faculties, structural problem-solving skills, and a highly collaborative team-player mindset – Mandatory