Staff/ Principal Design Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Verification Environment Development
• Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
• Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
• Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
• Coverage & Quality Assurance
• Implement functional coverage models and analyze results to identify gaps in the verification process
• Drive designs toward 100% verification closure through comprehensive test development
• Contribute to verification methodology improvements and best practices
• Debug & Cross-Functional Collaboration
• Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
• Apply analytical skills and debugging techniques to solve intricate verification challenges
• Collaborate effectively in a fast-paced, team-oriented R&D environment
  

• Bachelor's degree in Electrical Engineering or related technical field
• 5+ years of proven experience in ASIC verification within the semiconductor industry
• Hands-on experience developing components within complex verification environments using SystemVerilog
• Strong working knowledge of standard verification methodologies, specifically UVM
• Sharp analytical mind with passion for debugging and technical problem-solving
• Excellent communication skills with ability to thrive in collaborative R&D environments
  
  

• Master's degree in Electrical Engineering or related field
• Familiarity with Formal Verification or Emulation flows
• Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
• Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL
• Experience with assertion-based verification and constrained-random testing
• Background in connectivity or networking silicon verification