Back End Engineer

A highly successful, global semiconductor startup developing advanced, high-speed communication microchips optimized for next-generation, hyper-scale data centers.

The company engineers cutting-edge silicon architectures that handle massive data throughput under strict low-power and high-frequency constraints.

Comprising around 70 elite professionals, this agile organization combines a fast-paced startup culture with deep-tech hardware execution, providing an exceptional environment for top-tier chip design experts to build architectures that power global cloud infrastructures.

The company is located in Tel Aviv (highly accessible via primary train lines) and operates on a hybrid model with flexibility for two days of remote work.

Position Overview-

• Principal Physical Design (Backend) Engineer taking comprehensive ownership over the complex design, high-frequency execution, and structural implementation of advanced communication chips.
• Designing and ramping up a comprehensive, end-to-end full RTL-to-GDSII flow for highly advanced, small-geometry technology nodes.
• Managing technical collaborations, design-rule exchanges, and sign-off validations with external vendors, IP suppliers, and global foundry partners.
• Architecting sophisticated low-power implementation strategies, cross-coupling frequency scaling with strict thermal and energy efficiency budgets.
• Serving as the primary technical authority for backend synthesis, placement, routing, and physical verification for high-complexity, multi-million gate blocks.
• Silicon & Engineering Ecosystem ASIC Physical Design, Full RTL2GDSII Flow, High-Frequency Layouts, Low-Power Design, Logic Synthesis, Formality, Timing Constraints, IP Integration, Memory Compilers, DFT, Floorplanning, PG Mesh, Place & Route (P&R), Static Timing Analysis (STA), and IR-Drop.

Requirements-

• B.Sc. degree in Electrical Engineering, Electronics Engineering, or a highly related quantitative academic discipline (Mandatory).
• 8+ years of proven, hands-on professional experience in ASIC Physical Design (Backend implementation) (Mandatory).
• Comprehensive, deep technical expertise in executing a complete RTL-to-GDSII flow across advanced, nanometer-scale silicon nodes (Mandatory).
• Proven practical background in Logic Synthesis, formal verification (equivalence checking), and complex IP/Memory Compiler integration (Mandatory).
• Solid hands-on experience authoring structural design constraints, building robust Floorplans, and configuring PG Meshes (Mandatory).
• Practical engineering specialization in Low-Power design methodologies—encompassing definition, physical implementation, and multi-rail validation (Mandatory).
• Authoritative technical command over Static Timing Analysis (STA) and comprehensive IR-Drop debugging (Mandatory).
• Exceptional systems-thinking capability, high technical autonomy, and the communication skills required to effectively steer workflows with external global vendors.