Backend Software Engineer

A prominent global provider of end-to-end ASIC design architectures and comprehensive turnkey manufacturing solutions tailored for pioneering fabless companies and global OEM manufacturers.

The company specializes in transforming abstract concepts into highly advanced System-on-Chip (SoC) micro-architectures, backing them with complete supply-chain execution from silicon validation to mass physical production.

The company is located in the Sharon region and operates on a hybrid work model allowing for two days of remote work.

Position Overview-

• Senior Physical Design (Backend) Engineer joining an elite silicon engineering division to own high-complexity physical implementation pipelines for advanced SoC nodes.
• Driving complete block-level and top-level physical implementation execution, transforming synthesized netlists into tape-out ready silicon layouts.
• Resolving highly intricate signal integrity, power distribution, and nanometer-scale geometry bottlenecks across multi-layer silicon substrates.
• Acting as a principal technical authority on high-frequency timing resolution, clock distribution architectures, and structural sign-off verification.
• Collaborating closely with Front-End RTL designers, DFT engineers, and global foundry teams to ensure optimal yield and absolute post-silicon reliability.
• Silicon & Engineering Ecosystem- ASIC Physical Design, Backend Engineering, SoC (System on Chip), Floorplanning, Place & Route (P&R), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Timing Closure, Power Grid Analysis, IR-Drop, Physical Verification, LVS, and DRC.

Requirements

• B.Sc. degree in Electrical Engineering or Electronics Engineering from a highly recognized academic university (Mandatory).
• 6+ years of proven, hands-on professional experience in ASIC Physical Design (Backend implementation) (Mandatory).
• Comprehensive, production-grade technical expertise in Floorplanning, Placement, and routing (Place & Route) workflows (Mandatory).
• Deep structural command over Static Timing Analysis (STA) and achieving Timing Closure on complex, high-frequency design constraints (Mandatory).
• Proven practical experience with Clock Tree Synthesis (CTS) architectures and optimization (Mandatory).
• Hands-on engineering background performing Power Grid Analysis, power delivery network optimization, and structural IR-drop debugging (Mandatory).
• Extensive, direct technical experience running physical verification suites and debugging intricate LVS and DRC constraints (Mandatory).
• High technical autonomy, excellent analytical problem-solving capabilities, and a meticulous, sign-off-oriented engineering mindset.