CAD Logic Equivalence Checking (LEQ) Engineer

Summary
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Apple’s CAD Hardware Tech team are responsible for automating processes in designing Apple’s chips which power everything from Apple Watch and Apple TV to iPhone and iPad. We have outstanding career opportunities for interns interested in applying their software knowledge towards developing Apple’s ground breaking methodologies. Working among the industry's best, we’re looking for those with talent and ambition to innovate the way we design computer chips, to provide the next technological leap and improve customer experiences.

Description
We are seeking a CAD LEQ (Logical Equivalence Checking) Engineer to develop, deploy, and support equivalence checking methodologies across complex SoC programs. This role focuses on ensuring functional correctness between RTL, synthesized netlists, and post-implementation designs, while driving scalable, robust sign-off flows.

Responsibilities

• Own and maintain LEQ sign-off methodology across RTL-to-GDS flows
• Develop and support flows using tools such as Cadence Conformal and equivalent industry solutions
• Drive power-aware equivalence checking including CPX flows
• Enable ECO flows, ensuring safe and correct implementation of late-stage design changes
• Debug equivalence failures and perform root-cause analysis across RTL, synthesis, and PnR stages
• Collaborate with design, synthesis, PD, and power teams to resolve mismatches and improve convergence
• Optimize runtime, capacity, and scalability of LEQ flows for large SoCs
• Define best practices, guidelines, and automation for LEQ usage across projects
• Partner with EDA vendors to resolve tool issues and drive feature improvements
  
  

• BSc/MSc in Electrical Engineering or Computer Science
• 5+ years of experience in VLSI industry
• Strong understanding of: RTL design, Synthesis and netlist transformations, low-power design ( UPF concepts)
• Hands-on experience with LEQ tools ( Cadence Conformal , Synopsys Formality )
• Strong debugging and scripting skills ( TCL, Python )
  
  

• Experience with power-aware LEQ and low-power verification flows
• Familiarity with synthesis and PnR flows
• Experience in large-scale SoC environments and multi-site collaboration
• Exposure to ECO flows and late-stage sign-off methodologies
• Experience working with EDA vendors and driving tool improvements