Senior Logic Design Engineer

Job Details

Job Description:

Work Model: Hybrid

This position follows a hybrid work model, with 3–4 days per week working from the office.

The team is based in Haifa.

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

Role

We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs. In this role, you will:

• Design and Develop: Create logic design, RTL, and simulation for IP blocks, functional units, and subsystems.
• Architectural Contribution: Participate in defining architecture and microarchitecture features for the designed block.
• Mixed-Signal Expertise: Apply advanced strategies, tools, and methods for mixed-signal designs, including analog behavior modeling and circuit simulation, to write RTL and optimize logic.
• Performance Optimization: Ensure designs meet power, performance, area, and timing goals while maintaining integrity for physical implementation.
• Verification and Quality Assurance: Review verification plans, validate design features, and implement corrective measures for failing RTL tests.
• Customer Support: Collaborate with SoC customers to ensure seamless integration and high-quality IP delivery.
  
  

• 7+ years of industry experience delivering complex, high-performance integrated solutions and driving them through mass production.
• Proven expertise in SerDes and PHY design, including RTL development and firmware implementation, is highly advantageous.
• Strong background in interfacing with communication standards and optimizing serial link chip architectures for power, performance, and area targets.
• Hands-on post-silicon experience in validating and refining design outputs through debugging and corrective measures.
• Additional experience contributing to system architecture definition and applying digital signal processing techniques is considered a plus.
• B.Sc. or M.Sc. in Electrical Engineering.