VLSI Backend Team Leader

An established, global semiconductor corporation that designs high-performance multimedia processors, wireless communication chipsets, and digital signal processing (DSP) IP architectures for the microelectronics and artificial intelligence markets.

The company provides complex system-on-chip (SoC) microarchitectures and specialized processing cores deployed across millions of electronic units worldwide.

Operating an extensive engineering ecosystem with hundreds of professionals globally, the local design center drives end-to-end silicon implementation from architectural inception to tape-out.

The company is located in the Center District (train-accessible) and operates on a hybrid model of two days office-based.

Key Responsibilities-

• Leading, mentoring, and scheduling deliverables for an agile physical design engineering team to meet strict tape-out timelines.
• Executing full-cycle physical design tasks including logical synthesis, floorplanning, Place and Route (P&R), and clock tree synthesis.
• Formulating and analyzing Static Timing Analysis (STA) constraints across multi-corner multi-mode configurations to guarantee functional closure.
• Authoring, modifying, and maintaining automated physical design and sign-off flows utilizing custom Python and TCL infrastructure scripting.
• Partnering with RTL design, verification, and foundry integration teams to resolve structural anomalies, power grid drops, and signal integrity risks.

Requirements-

• B.Sc. in Electrical Engineering, Electronics Engineering, or an equivalent academic discipline (Mandatory).
• 5 years of professional engineering experience operating as a VLSI Backend / Physical Design Engineer (Mandatory).
• Proven track record in a formal management or technical team leadership role within a VLSI physical design group (Mandatory).
• Comprehensive hands-on experience running advanced digital synthesis, Place & Route (P&R), and Static Timing Analysis (STA) flows (Mandatory).
• Deep technical familiarity driving complete RTL-to-GDSII pipelines for highly complex, high-frequency digital designs (Mandatory).
• Practical production-grade experience engineering chips on advanced geometries at 7nm and below fabrication nodes (Mandatory).
• Proficient scripting capabilities utilizing TCL or Python to automate internal design house workflows (Mandatory).
• Direct engineering exposure to SoC physical integration methodologies or practical knowledge of RTL logic design (Verilog / SystemVerilog) is a distinct advantage.