Senior PIC Layout & Tape-Out Engineer

Company Description

MoRF is developing a silicon-compatible photonics platform that brings high-speed, low-energy electro-optic performance into standard silicon manufacturing. Its proprietary material stack and process flow are designed to integrate with existing silicon infrastructure, avoiding the cost, yield, and scale limitations of specialized photonic fabs. MoRF’s first target is high-bandwidth optical modulation for data centers and telecom, with longer-term applications in quantum and RF photonics. 

Role Description

We are looking for a Senior PIC Layout & Tape-Out Engineer to join as one of the first photonics hires in our startup. This person will own the physical implementation of our photonic integrated circuits, from early layout exploration through foundry-ready GDS, DRC/LVS closure, mask review, and tape-out. This is a hands-on technical ownership role. The right candidate should be able to work directly with photonic device designers, RF/electrical engineers, packaging engineers, test engineers, and foundry partners to turn device concepts and circuit schematics into manufacturable, testable, and scalable PIC layouts. 

Responsibilities

•  Own PIC layout implementation from concept through tape-out, including block-level layout, chip-level floorplanning, hierarchy, routing, verification, and final GDS/OASIS preparation.
• Translate photonic-device specifications, schematics, and layout intent into manufacturable layouts for waveguides, couplers, MZIs, rings, modulators, photodetectors, heaters, grating couplers, edge couplers, test structures, and optical routing.
• Create and maintain reusable PCells and layout libraries for key photonic building blocks such as waveguides, bends, tapers, couplers, splitters, modulators, gratings, pads, and test structures.
• Perform waveguide routing while meeting optical-connectivity, bend-radius, spacing, loss, crosstalk, density, and process-design-rule constraints. Breaking the Silicon Wall
• Integrate photonic layouts with electrical and RF interfaces, including electrodes, heaters, pads, GSG structures, metal routing, ESD-related constraints, keepouts, and packaging interfaces.
• Run, debug, and close DRC, LVS, optical connectivity, hierarchy, density/fill, and foundry signoff checks. Prepare tape-out-ready GDS/OASIS data and support mask review, foundry submission, waiver discussions, and post-submission issue resolution.
• Work with device and simulation engineers to make layout tradeoffs that preserve optical, RF, thermal, and manufacturing performance.
• Build and improve the company’s PIC layout methodology, including naming conventions, hierarchy rules, PCell standards, layout review checklists, tape-out documentation, and version-controlled design flows.
• Support test-chip planning by creating layout structures for process monitors, cutbacks, calibration devices, RF/EO test structures, and wafer-probe access.
• Help establish the startup’s internal layout infrastructure so future designs become faster, cleaner, and less dependent on manual heroics. 

Requirements

● B.Sc., M.Sc., or equivalent practical experience in electrical engineering, photonics, physics, microelectronics, or a related field.

● Hands-on experience with custom IC or photonic IC layout.

● Strong proficiency with Cadence Virtuoso or a comparable professional layout environment.

● Experience working with foundry PDKs and design-rule manuals.

● Hands-on experience running and debugging DRC and LVS.

● Familiarity with GDSII/OASIS workflows, hierarchical layout, cell libraries, mask layers, layer maps, and tape-out preparation.

● Understanding of photonic layout concepts, including waveguides, bends, tapers, grating couplers, edge couplers, splitters, MZIs, rings, heaters, modulators, and photodetectors.

● Ability to translate incomplete or evolving design intent into clean, reviewable, manufacturable layout.

● Experience with layout automation or scripting using Python, SKILL, KLayout, gdsfactory, IPKISS, Luceda, or similar tools.

● Strong attention to detail and the ability to manage complex layouts under tape-out schedule pressure. ● Comfort working in an early-stage startup environment where processes are still being built and engineers are expected to own problems end-to-end.