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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.

מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.

Verification Engineer

Dialog

תל אביב - יפו

Verification Engineer

Dialog

תל אביב - יפו
מלאה, היברידית
22,000-32,000 ₪ (הערכה מבוססת AI)
זוהי הערכת טווח שכר מבוססת AI ולא פרסום של המעסיק

A world-class Semiconductor technology company is expanding its VLSI group to drive the next generation of AI chips for edge devices.

By merging deep software and hardware expertise, the organization develops high-performance processors that enable smarter, more efficient autonomous machines.

The company is located in Central Israel and operates a hybrid work model with two days of remote flexibility.

Role Overview:

Strategic Verification: Partnering closely with Architecture and Design teams to develop comprehensive testcases for complex NN (Neural Network) processor blocks and SoC flows.
Environment Ownership: Maintaining and scaling a sophisticated verification environment based on the UVM methodology.
End-to-End Vision: Ensuring full functional and performance integrity by understanding the complete system flow and development lifecycle.
Complex Logic Validation: Identifying and resolving deep technical bottlenecks within the ASIC design to ensure production-ready quality.
Global Collaboration: Working within a high-talent, international engineering environment, communicating regularly with global teams to align on verification standards.

Requirements:

B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related field from a leading university – Mandatory.
3+ years of professional experience in ASIC Verification or Design – Mandatory.
Deep proficiency in SystemVerilog and UVM methodology – Mandatory.
Proven experience with SoC-level verification – Significant Advantage.
Strong problem-solving skills and the ability to analyze complex hardware architectures.
High-level English communication skills (verbal and written).