Senior RTL Design Engineer, Google Cloud

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience with RTL development for ASIC subsystems using Verilog.
• Experience with speed interfaces such as Peripheral Component Interconnect Express (PCIe), InfiniBand, and their low latency, security, and reliability principles.
• Experience with micro architecture, design, verification, logic synthesis, and timing closure.
  
  

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl).
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high performance and low power design techniques.
• Knowledge of Field Programmable Gate Array (FPGA), emulation platforms, and SoC architecture.
• Knowledge of assertion-based formal verification.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead an ASIC subsystem.
• Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
• Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
• Define efficient micro-architecture and block partitioning/interfaces and flows.
• Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .