Design Engineer

Summary

These roles sit at the heart of Apple’s Silicon Technologies and Wireless Connectivity groups. Whether focusing on Wireless ICs, Image Signal Processing (ISP), Power Management, or PHY/Logic design, the core mission is the same: architecting and implementing next-generation, power-efficient SoCs that fuel the entire Apple ecosystem.

Description

Apple is looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and 'crisis times.' Beyond technical excellence, successful candidates are:

Intrinsically, see the importance of every detail in 'elegant solutions.'

Excellent interpersonal and communication skills to work across diverse functional areas.

Schedule-driven with a desire to solve challenges that have never been solved before.

Responsibilities

• Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
• Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
• Front-End Flow Management: Take ownership of 'correct-by-construction' design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
• Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
• Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.
  
  

• B.Sc. or M.Sc. in Electrical Engineering (EE) or Computer Engineering (CE).
• 3-6+ years of hands-on experience in ASIC/Digital Logic design.
• Expert-level SystemVerilog/Verilog; Proficiency in C/C++ and MATLAB.
• Strong ability in Python, Perl, or Tcl for design automation and flow management.
• Low-power design (UPF, clock/power gating), High-bandwidth pipelines, and DFT.
  
  

• Specialized Domain Opportunities
• Depending on the specific team, candidates will focus on one of the following high-impact areas:
• Wireless Connectivity: Developing signal processing intensive SoCs (Modem, Radar) for PHY layer algorithms.
• Image Signal Processing (ISP): Implementing cutting-edge HDC pixel technology for iPhone camera systems.
• Power Management: Designing complex power state transitions, boot processes, and HW security solutions for compute SoCs.
• PHY Logic Design: Developing AMS (Analog Mixed Signal) PHYs and establishing CAD design methodologies.