Design Verification Manager – IP Group

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About The Role

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the world’s largest AI clusters.

Key Responsibilities

• Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
• Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
• Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
• Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
• Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle
  
  

• B.Sc. in Electrical Engineering, Computer Engineering, or a related field
• 10+ years of proven hands-on experience in ASIC verification, with at least 2+ years in a technical leadership or people management role
• Deep hands-on expertise in architecting complex small-to-medium (IPs, blocks, sub-systems) verification environments from scratch
• Expert-level knowledge of verification methodologies, specifically UVM
• Proven ability to manage project timelines, resource allocation, and the professional growth of IP verification team members
• Exceptional interpersonal skills with the ability to navigate a fast-paced, collaborative R&D environment and influence stakeholders
  
  

• Extensive experience with SV-UVM verification of complex IPs and subsystems
• Experience implementing Formal Verification strategies at the block level
• Proficiency in Python/Tcl for environment automation and a track record of improving verification productivity
• Deep understanding of high-speed industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL