Senior/ Staff Front-End CAD Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.

Key Responsibilities

• Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
• Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
• Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
• Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows
  
  

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience in relevant industries
• Proven experience in Python and Tcl within a Linux/Unix environment
• Knowledge and experience in Verilog and/or System Verilog
• Very good communication skills
  
  

• Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis
• Hands-on experience with industry-standard tools for lint, synthesis, simulation
• Experience with version control systems (Git) and compute cluster management (LSF/SGE)