Senior SerDes System Engineer

Job Details

Job Description:

We are seeking an experienced Senior SerDes System Engineer to lead the design, development, and optimization of high‑performance SerDes and DSP‑based system solutions for next‑generation products. This role requires deep system‑level understanding, strong algorithmic expertise, and close collaboration with architecture and hardware teams.

In This Role, You Will

• Lead the design and development of SerDes system models, DSP algorithms, and signal‑processing blocks.
• Define system and algorithm specifications aligned with performance, power, and reliability requirements.
• Perform system‑level modeling, simulation, and trade‑off analysis across power, performance, and area.
• Drive algorithm tuning, validation, and performance optimization across multiple stages of product development.
• Collaborate with digital architecture and RTL teams to translate system models into efficient hardware implementations.
• Support implementation of DSP and SerDes subsystems in RTL and ensure successful integration into full‑chip designs.
• Develop post‑silicon validation strategies, create test and debug scripts, root‑cause complex system issues, and drive performance optimization in lab environments.
• Research and apply advanced DSP, equalization, and ML/AI‑based techniques to improve link performance and robustness.
• Act as a technical leader, contributing to roadmap definition, cross‑team alignment, and industry best practices.
  
  

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Minimum 8+ years of hands‑on experience delivering complex, high‑performance SerDes and PHY solutions, from architecture and design through silicon validation and mass production.
• Strong practical experience with SerDes and PHY architectures, including DSP and algorithm development for equalization, calibration, adaptation, and system‑level optimization.
• Deep understanding of high‑speed serial communication standards and techniques for end‑to‑end link performance optimization (signal integrity, jitter, noise, and margin analysis).
• Proven post‑silicon validation and debug experience, including performance characterization, root‑cause analysis, and design refinement.
• Experience with logic design and RTL development; familiarity with firmware or embedded software is a strong advantage.
• Demonstrated ability to work at the system level, collaborate across cross‑functional teams, and drive technical decisions in complex environments.