Layout Physical Design Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

At NVIDIA Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet Layout owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!

What You'll Be Doing

• Be part of a cross-business-unit team and own the high-speed IP integration.
• Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
• Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
• Define and implement efficient, high-quality Full Chip/Chiplet physical design tools, flows, and methodologies.
• Gain hands-on experience implementing the partition-level BE design (RTL2GDS).
  
  

• B.S. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience.
• At least 3 years of relevant experience.
• Proven expertise in P&R and Layout tools, TCL scripting, and Netlist-to-GDSII flow.
• Great teammate, responsible, and motivated.
• Experience in unit and top-level floor planning, full-chip clock tree, power grid planning, and DRC/LVS.