Senior Integration Engineer, Senior Integration Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.

Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are now looking for a versatile, fast learner, and highly motivated FE Integration and EDA Tools Engineer! As a member of our Switch organization, you will be part of front‑end integration and EDA flows for a high‑performance, low‑power switch chip. our FEI team drives methodologies, automation, and quality for our front‑end implementation and cd/ci, working closely with architecture, design, verification, and backend teams. This position offers you the opportunity to have real impact in a dynamic, technology‑focused company influencing future switch product lines.

What You'll Be Doing

• Driving front‑end integration of major blocks in a pioneering Ethernet switch ASIC, from RTL handoff through synthesis and signoff checks.
• Building, maintaining, and improving EDA flows and methodologies for the Switch org (lint, CDC/RDC, formal, synthesis/ULS, FE‑DCT/FE‑FC and related front‑end signoff flows).
• Working closely with logic design and micro‑architecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
• Partnering with DV, BE, and CAD/flow teams to ensure robust, scalable, and efficient front‑end implementation across the project.
• Developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
• Debugging complex tool, flow, and design issues; driving root‑cause analysis and long‑term methodology improvements.
  
  

• A Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 10+ years of experience in front‑end integration, ASIC design, or EDA/methodology for high‑performance semiconductor designs.
• Hands‑on experience with front‑end implementation flows: synthesis, STA at FE level, lint, CDC/RDC, formal equivalence, and related signoff checks.
• Strong familiarity with industry‑standard EDA tools (for example: Synopsys Design Compiler / Fusion Compiler, Cadence Genus, CDC/lint/formal tools) and with complex SoC/ASIC build flows.
• Strong communication and interpersonal skills, and comfort working in a dynamic, global team environment.