Physical Design Chip Top Expert

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Chip Top Expert to Lead Chip Level PD Execution with full SoC CoT end to end Engineering Chip development (RTL to GDS).

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the world’s largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

• SoC Top level Ownership and oversee the Chip convergence.
• Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
• Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
• Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects
  
  

• B.Sc. or M.Sc. in Electrical Engineering
• 15+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills
• Deep expertise in Chip Top Level activities and signoff, RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration
  
  

• Deep understanding of Power & Noise analysis (EM/IR)
• Experience with DFT (Design for Test) integration
• Background in high-speed interfaces or data center protocols