Senior Digital Design Engineer

About the Business Unit:

Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer.

Within the Wireless Internet of Things group, Ceva is offering you the chance to be a member of our Hardware Radio team in Athens, which was established after the acquisition of MEICSi by Ceva.

About the Role:

In this role, you will contribute to the development of next‑generation wireless communication technologies, including advanced MIMO Wi‑Fi and Bluetooth transceivers. You will join an innovative and highly skilled team responsible for digital RF design, working at the intersection of architecture, algorithms, hardware, software, and system engineering. Together, you will help shape state‑of‑the‑art connectivity solutions that power tomorrow’s connected devices.

Responsibilities:

Own the design and verification of digital blocks for advanced RF transceivers, ensuring high performance and robustness.

Collaborate closely with system, algorithms, and baseband teams to define specifications, interfaces, and functional requirements.

Develop clear and comprehensive technical documentation for the designed modules, including architecture, interfaces, and verification details.

Support post‑silicon bring‑up, verification, and validation activities in collaboration with cross‑functional teams to ensure successful product integration and performance.

Requirements:

• PhD or Master’s degree in Electrical & Computer Engineering or equivalent field with specific knowledge of digital circuit design.
• Senior level experience with more than 5 years of experience on digital ASIC or FPGA design. Experience with DSP blocks, digital blocks for mixed-signal circuits (ADPLL, ADC, etc.), RF calibration digital blocks, SPI and APB/AHB interfaces.
• Knowledge of System Verilog, Cadence Xcelium simulator, lint and CDC checks, synthesis tools, STA concepts and constraint definition, constrained random verification principles, gate level simulation, and design for DFT/ATPG support.
• Knowledge of Matlab/Python for algorithm specification and bit accurate verification of RTL vs system model.
• Knowledge of scripting languages (Tcl, bash, etc.) and Linux environment.
• Experience writing reports and technical documentation.
• Team player with good verbal and written communication skills.
• Flexibility and dynamic thinking.
• Good organizational and prioritization skills.
• Fluency in English.

Advantage:

• Knowledge of Bluetooth and Wi-Fi protocols at PHY and MAC layer level.
• Experience with chip/platform bring-up, lab testing and validation.
• Knowledge of Python scripting for lab automation.
• Knowledge of RISC V based system architecture.