Design Verification Manager

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale. This is a unique opportunity to take on meaningful product ownership in a new site and help build our local engineering powerhouse from the ground up.

We are seeking a visionary Design Verification Manager to lead the quality and reliability strategy for our Israel R&D center. If you thrive on solving complex, uncWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.harted challenges in deep-submicron processes, this role is for you.

About The Role

As a Design Verification Manager, you will be responsible for steering the verification roadmap, overseeing the development of complex testbenches, and ensuring our next-generation AI silicon meets the highest standards of excellence. Leading a team of talented engineers, you will tackle challenges at the unit, sub-system, and full-chip levels, playing a pivotal leadership role in delivering high-performance hardware for the world's largest AI clusters.

Key Responsibilities

• Lead and mentor a team of verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and sub-system levels
• Drive the creation and execution of comprehensive verification plans, ensuring all functional requirements are met on schedule for complex digital designs
• Oversee the architecture and maintenance of multiple verification strategies including DV using SV-UVM, Formal and Emulation
• Define functional coverage goals and quality metrics, driving the team toward 100% verification closure and sign-off
• Partner closely with Design, Architecture, and Backend teams to align on specifications, root-cause complex bugs, and optimize the hardware development cycle
  
  

• B.Sc. in Electrical Engineering from a leading academic institution
• 15+ years of proven experience in ASIC verification, with at least 5+ years in technical leadership or people management role
• Deep hands-on expertise in architecting complex verification environments for both small-scale (IPs, blocks) and large-scale (full chip, SoC) designs
• Expert-level knowledge of verification methodologies
• Proven ability to manage project timelines, resource allocation, and professional growth of team members
• Exceptional interpersonal skills with ability to navigate fast-paced, collaborative R&D environments and influence stakeholders
  
  

• Experience with SV-UVM verification of complex systems
• Experience implementing Formal Verification or Emulation strategies at team level
• Proficiency in Python/Tcl for environment automation with track record of improving verification productivity
• Deep understanding of high-speed industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL