Tech Lead Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Tech Lead Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, architecting the verification environments that ensure our next-generation AI silicon is flawless.

As a Tech Lead Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests—you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

• Verification Environment Architecture & Development
• Design and develop comprehensive ASIC verification environments across all levels—from unit-level and subsystems to full-chip integration
• Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
• Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
• Quality Assurance & Debug Excellence
• Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
• Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
• Ensure verification closure through rigorous coverage analysis and assertion-based verification
• Cross-Functional Collaboration & Technical Leadership
• Partner with design and system architects to solve intricate hardware verification challenges
• Work alongside world-class teams where knowledge sharing and technical excellence are the standard
• Contribute to verification methodology improvements and automation initiatives
  

• Bachelor's degree in Electrical Engineering or related technical field
• 7+ years of proven experience in ASIC verification within the semiconductor industry
• Demonstrated expertise in building complex, scalable verification environments from scratch
• Deep knowledge of standard verification methodologies, specifically UVM (or OVM)
• Expert-level command of SystemVerilog for verification
• Excellent communication skills and team-oriented mindset with ability to thrive in collaborative, high-stakes R&D environments
  
  

• Master's degree in Electrical Engineering or related field
• Knowledge or hands-on experience in Formal Verification and Emulation methodologies
• Proficiency in scripting languages such as Python or Tcl to streamline verification flows
• Experience with high-speed protocols (PCIe, Ethernet, CXL, UALink) and complex traffic patterns
• Background in connectivity or networking silicon verification
• Experience with advanced coverage techniques and constrained-random verification