Design Verification Engineer

Real Time Group, LTD., SW and HW Solutions Center is looking for an experienced Verification Engineer.

Job Responsibilities:

· Responsible for the full life cycle of verification - from verification planning to test execution, to collecting and closing coverage.

· Plan the verification of complex digital blocks, containing embedded processors, by fully understanding the design specification and interacting with design & SW engineers to identify important verification scenarios.

· Create an automated constrained-random verification environment using System Verilog , C/C++ programs & scripting languages.

· Develop a constrained-random verification environment using UVM.

· Identify and write all types of coverage measures for stimulus and corner-cases.

· Debug tests with design engineers to deliver functionally correct design blocks.

· Collaborate closely with design and verification engineers in active projects and perform hands-on verification.

Must Have Requirements:

• BSc. in Electrical/Electronic Engineering.
• At least 3 year experience as Verification Engineer.
• Knowledge in verification methodologies, tools (simulators , coverage tools, assertions , formal, etc.) and techniques.
• Broad Knowledge in System Verilog & Verilog.
• Knowledge of UVM.
• Good knowledge of Unix environment and script languages : Python, C Shell, Perl.
• Basic knowledge of C/C++ programing.
• Methodological approach to building of verification environment and test plan.
• Methodological approach to the verification tasks planning and execution.

Nice to Have:

• Experience with embedded processor verification.
• Ability to work well in a team