Memory Design Engineer

Summary

Do you have a passion for crafting entirely new solutions?

Be a part of a world-class silicon design team that delivered an incredible high-performance chip for our flagship products.

As part of our Digital Custom Group (DCG), you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the foundation that allows us to bring customers experiences they’ve never before envisioned!

This is a highly visible role at the heart of a silicon design effort, making a critical impact by delivering products to market quickly. Your designs will strongly influence CPU / GPU / SoC / Neural Engine / Camera designs in Apple's Custom Silicon group.

Description

Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role in getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, work with a team of hardworking engineers, and implement groundbreaking techniques of Machine Learning, Circuit design in Apple’s marquee products.

Responsibilities

• As an SRAM Circuit Designer for the Digital Custom Group, you will perform the following:
• Design and implement custom digital circuits for SRAM design.
• Work with an extraordinary logic/architecture team to formulate design specifications.
• Define architecture/topologies optimizing for power, timing, area, and yield.
• Schematic capture, simulations/analysis, and margin verifications.
• Functional equivalency and DFT modeling.
• Work with the layout team to create optimal GDS.
• Verify extracted GDS meets design specifications.
• Backend verification, IR/EM.
• Write RTL, validate use-cases, and verify against design schematics.
• Support post-silicon effort to enable productization.
  
  

• BS and a minimum of 7 years of relevant industry experience
• MSc is an advantage
  
  

• Work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage, and high performance.
• Knowledge of Cache design/architecture, memory hierarchy is a huge plus.
• Working knowledge of RTL modeling.
• Solid understanding of industry-standard design tools.
• Deep understanding of nanometer device physics, leakage mechanisms, technology interactions with device behavior.
• Ability to devise experiments and analyze data for silicon debug.
• Machine Learning algorithms (ML) and scripting is a big plus.