Verification Engineer

A high-growth Semiconductor startup developing a revolutionary chip architecture for next-generation AI compute-acceleration. The company is building groundbreaking solutions designed to power the world's most advanced Large Language Models (LLMs) and inference engines.

With a focus on ultra-high performance and efficiency, they are redefining the hardware foundation of Artificial Intelligence, working at the absolute cutting edge of the silicon industry.

Located in the Central District (ideally situated near major public transport hubs), the company operates a hybrid model with one day of remote work per week.

Role Overview -

• Joining an elite team responsible for the verification of a high-performance controller ASIC.
• Defining architecture and developing advanced Verification Environments and flows from scratch.
• Working across Block-level, Subsystem, and Full-chip verification levels.
• Developing Coverage-driven verification strategies and building sophisticated automation infrastructure.
• Collaborating closely with Design, Architecture, Algorithms, and Software teams to ensure flawless logic execution.
• Leading the creation of comprehensive test plans and functional coverage closure for multiple complex blocks.
• Debugging intricate logic interactions, multi-clock structures, and high-speed data paths.

Requirements -

• B.Sc. in Electrical Engineering or a related field – Mandatory.
• 5 years of professional experience as a Verification Engineer – Mandatory.
• 3 years of hands-on experience with SystemVerilog and UVM – Mandatory.
• Strong understanding of Coverage-driven verification methodologies.
• Proven experience working in Linux environments.
• Exceptional English (written and verbal) for technical documentation and collaboration.
• Deep diagnostic skills and a methodical approach to complex debugging.