ASIC Design & Integration Engineer

Summary

Apple is a place where extraordinary people capture to do their best work. Together we craft products and experiences people once couldn’t have imagined — and now can’t imagine living without. If you’re motivated by the idea of making a real impact, and joining a team where we pride ourselves in being one of the most diverse and inclusive companies in the world, a career with Apple might be your dream job.

The Apple design team is looking for an expert engineer to develop IP. In this Role you will get to handle micro-architecture definitions, RTL coding, block level simulations and implementation. Role expectations include working with partner design teams, verification, platform architecture and integration teams to define the IPs micro architecture, implement the required HW and integrate it into multiple sub-systems in Apple SoCs.

If you are looking for an exciting technical role with a broad system view in a complex, control-oriented IPs, this could be a phenomenal opportunity for you.

The role is relevant for all Apple sites: HRZ, Haifa

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

Minimum Qualifications

• 3+ proven experience in digital design
• IP Integration: Integrate third-party or internal IP blocks into a subsystem and SoC
• RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are accurately implemented
• Top-Level Assembly: Develop and maintain Subsystem top level RTL, wrappers, and interconnects
• Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality
• Build and Test Infrastructure: Develop and maintain automated build and regression systems for integration
• Design Constraints: Define and validate synthesis and timing constraints (SDC files)
• Timing Closure: Work closely with physical design and STA teams to achieve timing closure at top level
• Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up and debug
• Debug: Debug failures and resolve using problem-solving skills
• Documentation and Reviews: Create and maintain design documents and participate in design reviews
• BS.c / MS.c in EE/ CE
  
  

• This position requires detailed knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and net-list generation
• Solid understanding of digital logic design and RTL development (SystemVerilog, Verilog)
• Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence)
• Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB)
• Strong scripting skills (Python, Perl, TCL, Shell) for automation
• Good debugging and problem-solving skills
• Excellent communication and cross-functional collaboration