Design Verification Engineer - Camera

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.nnThe people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products.nnThe Pixel DV group works on complex, large-scale media IPs. We partner with our architecture and design teams to deliver high quality media IP and systems in order to meet the demanding requirements for excellent products, while boosting performance and meeting area and power goals, incorporating new high quality features.

Description

You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus.nApply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.nApply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance. nYou will work closely with the design and architecture teams from the early stages of feature definition, to ensure timely delivery of quality designs. nWorking with methods to accelerate verification time.nInvolvement with Post Silicon Validation and other verification teams.nCandidate should have good interpersonal and collaboration skills, to work with our partner Design and Architecture teams

Minimum Qualifications

+2 years experience in SoC Verification, media IP verification experience is a plusnYou will need to have advanced knowledge of SoC/Media IP architecture/design & in-depth knowledge of verification flow.nExpected to have a deep understanding and shown experience in advanced verification process, including dynamic and coverage based.nScripting and programming experience using several of the following: Python, Perl, e, SystemVerilog, C++, and TCL

Preferred Qualifications

Familiarity with verification environments, UVM, SystemVerilog – an advantage.nKnowledge of hardware acceleration – an advantage.