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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
We are a highly skilled development team of talented engineers, driving the development of Marvell's next-generation network switches.
Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification
What You Can Expect
- Drive functional verification of complex networking blocks using UVM/SystemVerilog.
- Develop and maintain advanced verification components and testbenches.
- Collaborate with cross-functional teams including architecture, design, firmware, and post-silicon.
- Contribute to methodology and infrastructure improvements in a dynamic and innovative environment.
- B.Sc. or M.Sc. in Electrical/Computer Engineering
- 7+ years of hands-on experience in ASIC/RTL verification
- Strong background in SystemVerilog and UVM methodology
- Deep understanding of coverage-driven verification, object-oriented programming, and constrained random testing
- Excellent problem-solving skills and self-learning ability
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
במקום לחפש לבד בין מאות מודעות – תנו ל-Jobify לנתח את קורות החיים שלכם ולהציג לכם רק הזדמנויות שבאמת שוות את הזמן שלכם מתוך מאגר המשרות הגדול בישראל.
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שאלות ותשובות עבור משרת Senior Design Verification engineer
כמהנדס אימות תכנון בכיר ב-Marvell Technology, תהיה אחראי על הנעת אימות פונקציונלי של בלוקי רשת מורכבים באמצעות UVM/SystemVerilog, פיתוח ותחזוקה של רכיבי אימות מתקדמים וסביבות בדיקה, ושיתוף פעולה עם צוותים שונים כולל ארכיטקטורה, תכנון, קושחה ופוסט-סיליקון. בנוסף, תתרום לשיפור מתודולוגיות ותשתיות בסביבה דינמית וחדשנית.
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