Hardware Engineer

Who We Are

MA Capital is a proprietary trading firm specializing in systematic and high-performing discretionary strategies across multiple asset classes. We leverage advanced technology, quantitative research, and sophisticated models to capitalize on opportunities in global markets. Our culture is built on innovation, efficiency, and transparency. We are committed to providing liquidity and supporting fair, efficient markets, while ensuring our traders and professionals have flexibility, tools, and continuous learning opportunities to succeed.

Position Overview

We are seeking a skilled mid to senior-level FPGA engineer for a 1-month contract to build a

SystemVerilog-based HLS wrapper using the ExaNIC FDK TCP offload framework. The engineer will

design adapter-agnostic interfaces, CDC/FIFO modules between 10G network and PCIe clock

domains, and host integration via the ExaNIC FDK driver and C API. Target latency is under 100 ns

with line-rate performance.

Key Responsibilities

• Integrate ExaNIC FDK TCP offload across ExaNIC adapters.

• Develop SystemVerilog HLS wrapper and card-agnostic interfaces.

• Bridge AXI4-Stream ↔ Avalon-ST protocols with robust flow control.

• Implement CDC/FIFO modules using Vivado macros between 10G and PCIe clocks.

• Use ExaNIC FDK driver and C API for host ↔ card data/control.

• Build testbench with SVA and functional coverage.

• Produce performance analysis and optimization report.

Required Qualifications

• AXI4-Stream and Avalon-ST design and optimization.

• Cross-clock domain (CDC) design using Vivado macros.

• PCIe integration and driver-based communication.

• TCP offload engine integration.

• Strong C/C++ programming with hardware drivers.

• SystemVerilog with advanced constructs (interfaces, packages, assertions).

Big Plus

• Vivado HLS 2020.1 for C/C++ → RTL synthesis and optimization.

• Vivado 2025.1 automation, CDC/FIFO macros, and Tcl scripting.

• RTL simulation and waveform-driven debug.

• High-performance networking FPGA design experience.

Technical Environment

• Primary Language: SystemVerilog

• FPGA Platforms: ExaNIC Network adapters

• Tools: Vivado 2025.1 (RTL/CDC/FIFO), Vivado HLS 2020.1 (HLS C/C++)

• Framework: ExaNIC FDK with TCP offload

• Protocols: AXI4-Stream and Avalon-ST

• Host Communication: ExaNIC FDK driver and C API

• Clocks: 10G Ethernet ↔ PCIe host

• Target Latency: <100 ns wrapper path

Development Environment Access

• Contractor will have access to a development box with licensed Vivado 2025.1 and full ExaNIC FDK.

• Vivado HLS 2020.1 available for HLS synthesis.

• Full ExaNIC FDK source, documentation, and hardware access provided.

• Latency measurement excludes MAC/PCIe DMA.

• Results verified at line rate.

Contract Details

• Duration: 4 weeks (160 hours)

• Location: Remote

• Equipment: Licensed Vivado 2025.1, Vivado HLS 2020.1, full ExaNIC FDK, ExaNIC adapter hardware

• Performance Target: <100 ns wrapper latency with line-rate throughput.

• Deliverables: Source code, verification suite, performance report, and working project files.