Director Test Engineering

• Define and execute the long-term ATE test strategy and roadmap, ensuring alignment with R&D, operations, and business goals across all product generations.
• Develop and foster a culture of technical excellence, data-driven decision-making, and continuous improvement.
• Serve as a key technical liaison, reporting on product quality, yield performance, test cost, and reliability metrics.
• Direct the ATE Test Engineering team to deliver robust, high-coverage, and cost-effective test programs for wafer probe and final test on multiple ATE platforms (e.g., Teradyne UltraFLEX, Advantest V93K, RF Testers).
• Lead the Product Engineering team in driving significant yield improvement and cost reduction initiatives (e.g., test time reduction, multi-site efficiency, limit tightening) to meet COGS targets.
• Establish and implement best practices for Design for Test (DFT) and Design for Manufacturing (DFM) in collaboration with Design Engineering.
• Oversee complex failure analysis (FA) and root cause corrective action (RCCA) processes for engineering and production yield issues.
• Direct the Quality and Reliability Engineering (QRE) to define and execute comprehensive qualification plans (e.g., HTOL, HAST, ESD, Latch-up) according to industry standards (e.g., JEDEC, AEC-Q100).
• Ensure rigorous processes are in place for process change management, material disposition, and supplier quality.
• Be the final approver for all product release qualifications and ensure the product meets all internal and customer-specific quality and reliability requirements.
• Monitor field return data and drive cross-functional teams to implement corrective actions to improve Mean Time Between Failures (MTBF) and overall customer satisfaction.

Qualifications

Required

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 10 years of experience in the semiconductor industry across ATE Test and Product Engineering.
• Minimum of 5 years of experience managing multi-disciplinary engineering teams (Test, Product, Quality, or similar functions) in a senior leadership position.
• Understanding of semiconductor physics, yield ramp, statistical process control (SPC), and quality systems (ISO, AEC-Q100).
• Proven expertise in defining and executing strategies for high-volume manufacturing (HVM) yield entitlement and cost optimization.

Preferred

• Experience with specific market segments (e.g., Automotive, Industrial, Data Center, RF).
• Familiarity with advanced packaging technologies and their impact on test and reliability.
• Knowledge of advanced data analytics tools for large-scale production data (e.g., Spotfire, Tableau).