Staff Physical Design Engineer

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

As a Staff Physical Design Engineer, you will be responsible for implementing, optimizing, and verifying complex digital designs at the physical level. You will work closely with front-end designers, DFT engineers, and verification teams to deliver high-quality silicon solutions. Your primary focus will be on physical implementation, including floor planning, place and route (PnR), clock tree synthesis (CTS), timing closure, and physical verification for advanced node technologies (e.g., TSMC N5/N4P/N3).

What You'll Do

• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization for high-speed digital designs.
• Implement timing closure techniques, including clock skew balancing, delay optimization, OCV (on-chip variation) handling, and ECO (Engineering Change Orders).
• Conduct signal integrity, power integrity, IR drop, and electromigration analysis.
• Implement Optical Proximity Correction (OPC) litho shrink methodologies for advanced process nodes
• Optimize power and area using techniques like Multi-Vt optimization, clock gating, and power-aware synthesis.
• Conduct physical verification (LVS, DRC, DFM) to ensure compliance with foundry sign-off requirements.
• Collaborate closely with design, verification, DFT, and process engineers to resolve design and manufacturing issues.
• Drive scripting and automation efforts (Python, Perl, TCL, or equivalent) to improve design efficiency.
  
  

• 5+ years of experience in digital Physical Design (Backend) methodologies.
• Experience with advanced process nodes (e.g., TSMC N5, N4P, N3, etc.).
• Proficiency in industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, etc.).
• Strong understanding of floorplanning, clock tree synthesis (CTS), place & route (PnR), STA, IR drop analysis, EM analysis, and power optimization techniques.
• Experience with OPC litho shrink methodologies to optimize designs for advanced nodes.
• Familiarity with DFT concepts, including scan insertion, ATPG, and BIST, is a plus.
• Experience with multi-patterning techniques (LELE, SAQP) and signoff verification flows (DRC, LVS, DFM, EM/IR, PEX).
• Hands-on scripting experience (TCL, Python, or Perl) to automate design flows and analysis.
• Strong analytical and problem-solving skills, with a data-driven approach to troubleshooting design challenges.
• Preferred Experience: Work experience in TSMC N5, N4, N4P, N3, or other advanced FinFET process nodes.