SOC Architect -AI

Role Description

We are seeking an experienced SoC Architect – AI Acceleration (RISC-V and Compute Cluster Development) to lead the architecture and integration of Majestic’s compute subsystem.

In this role, you will define and optimize the RISC-V–based compute clusters, vector engines, and shared memory structures that power high-performance AI workloads.

You’ll collaborate closely with design, verification, compiler, and ML software teams to define architectures that maximize performance per watt while ensuring scalability across multiple generations of silicon.

This is a hands-on technical leadership role for an architect who thrives at the intersection of hardware design, parallel compute, and AI acceleration.

What You’ll Do

• Architect and define RISC-V compute clusters, including multi-core integration, interconnects, and memory subsystems.
• Design matrix multiplication and vector processing engines optimized for neural network and ML kernels.
• Define the ISA extensions, microarchitecture, and system-level interfaces supporting AI acceleration.
• Develop strategies for compute task mapping, thread scheduling, and shared cache (L3) utilization.
• Collaborate with compiler and ML runtime teams to ensure software–hardware co-optimization.
• Evaluate performance and power trade-offs across workloads using simulation and modeling.
• Define debug, trace, and performance-monitoring features at the compute-subsystem level.
• Work with SoC, memory, and I/O architects to ensure cohesive dataflow and system efficiency.
• Provide specifications and technical guidance for RTL, verification, and firmware implementation teams.
  
  

• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in SoC or compute architecture, with a focus on AI acceleration or high-performance compute.
• Deep understanding of RISC-V architecture, vector extensions, and parallel compute design.
• Experience with multi-core cluster integration, shared memory hierarchies, and cache coherency protocols.
• Familiarity with matrix multiplication engines, SIMD/vector processors, and AI kernel optimization.
• Strong background in embedded systems architecture, system-level performance modeling, and debug methodologies.
• Excellent analytical, problem-solving, and communication skills
  
  

• Experience designing custom RISC-V ISA extensions or AI-specific compute units.
• Hands-on work in neural network mapping, tiling, and kernel scheduling.
• Familiarity with AXI, UALINK, HBM, or chiplet-based architectures for scalable AI compute.
• Contributions to open-source RISC-V or AI compute frameworks.
• Proven success in first-silicon AI or HPC SoC programs.
• Understanding of compiler design and low-level ML operator optimization.