Physical Design Engineer

Chain Reaction designs and builds hardware that fuels advanced privacy technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure cloud computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data-analysis and real-time computing is acceleration – existing hardware cannot keep up with data processing needs. Chain Reaction’s products reshape how data is processed and used on a global scale, and we’re looking for the brightest people to join us.

We are looking for Physical Design Engineer

Roles And Responsibilities

• Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
• Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
• Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
• Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
• Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
• Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.
  
  

• B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering (hands-on IC layout/CAD experience also considered).
• 1–3 years of relevant industry experience or 3+ years for more senior candidates – both junior and experienced engineers will be considered.
• Hands on experience with layout and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
• Strong programming skills in SKILL, Python, TCL, Perl, and Shell (Csh, Bash).
• Ability to debug, optimize, and troubleshoot CAD flows and layout workflows.
• Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
• Strong communication and teamwork skills, with the ability to work independently in a dynamic, fast-paced environment.
  
  

• Prior experience as a Layout Engineer or EDA/CAD Physical Design Engineer in a semiconductor environment.
• Deep understanding of IC physical design and verification flows:
• Custom analog/digital layout, floorplanning, placement, routing
• DRC, LVS, ERC, parasitic extraction
• Physical verification and tapeout readiness
• Advanced SKILL programming for layout automation and productivity.
• Experience with tapeout preparation, design rule integration, and physical verification.
• Knowledge of PCells, parameterized devices, and layout generators.
• Proficiency in physical verification runset programming and maintenance, including customization of DRC/LVS/ERC decks and integration into design flows.
• Experience building automated regression environments for CAD/EDA flows in SKILL.
• Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.