Principal Engineer, Physical Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

HSCD team (High Speed Chip Design) has a 20 years of experience in designing the state of the art high performance processors, focusing on ARM cores and clusters, as well as other high performance designs, such as DSP. Team has a multi-disciplinary capabilities in both conventional physical design using the industry tools and accepted methodologies and full custom design required for achievement of high performance and low power characteristics. Team performs non standard solutions, global topics analysis contributing to the whole company.

IPs designed by team are used in Marvell products for 5G infrastructure, hyperscaler datacenter compute, CXL, etc.

What You Can Expect

For senior engineering candidates seeking a challenging and impactful role, this position at Marvell involves spearheading enhancements and providing critical support for our sophisticated Place and Route Flow, seamlessly incorporating industry-standard EDA tools. Your responsibilities encompass performing synthesis, place and route, as well as conducting in-depth timing analysis and closure on multiple complex and expert-level logic blocks. You will be at the forefront of developing and implementing intricate timing and logic ECOs. Collaboration is key, and you will work closely with the RTL design team to drive modifications that effectively resolve congestion and timing issues. Engaging with the global timing team, your role extends to debugging and resolving block-level timing issues observed at the partition level or full chip. Moreover, your influence will extend to interactions with tool vendors, where you'll drive improvements and conduct evaluations of new tools and functions. This role presents an exciting opportunity for seasoned engineers to contribute to cutting-edge projects in a collaborative and innovative environment at Marvell.

What We're Looking For

To be successful in this role you must:

• Have completed a Bachelor’s Degree in Electrical/Computer Engineering, Computer Science, or related fields and have 3-5 years of related professional experience OR a Master’s degree and/or PhD in Electrical/Computer Engineering, Computer Science, or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.
• Strong understanding of standard RTL to GDS flows and methodology
• Strong scripting skills in languages such as Perl, tcl, and Python
• In-depth understanding of digital logic and computer architecture
• In-depth knowledge of Verilog
• Good communication skills and self-discipline contributing in a team environment
• Strong problem solving ability
• Independent work driven by high motivation, initiative, creativity.