תפקיד Experienced Verification & Logic Designer

We are seeking a highly skilled Verification Engineer and Logic Designer to join our dynamic team.

Key Responsibilities:Develop and implement comprehensive verification plans for logic designsDesign and maintain testbenches for logic projectsConduct functional simulations and analyze results to ensure design integrityDebug and resolve issues identified during verificationCollaborate closely with design engineers to understand design intent and constraintsDesign and develop logic-based solutions using VHDL/Verilog Requirements:At least 4 years of hands-on experience in verification and logic designBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related fieldProven experience with VHDL logic design principles, including timing, area, and power implicationsExperience in creating complex designs, including coding and integrating third-party IpsStrong background in synthesis, place and route, and timing complianceProficiency in lab logic debugging methodologies such as ChipScope/SignalTap