Modeling of Architecture Team Leader

Back to careers

Description

About the CTO Unit:

The CTO organization defines the architecture of Ceva’s products and sets the company’s long-term technology vision. Working closely with multiple business units, the team ensures that breakthrough ideas become industry-leading IP and products.

About The Role

We are looking for a hands-on leader to head a small team that builds simulation models for our next-generation AI hardware and DSP. Modeling is done in several layers, from cycle-accurate, bit-exact block level modeling, to event-driven full IP system flows.

Your group’s mission is to take part in the exploration phase of a project, giving architects rapid, high-fidelity feedback so they can explore design options, and to perform algorithmic regression, detecting deadlocks, sweep parameters and features, and understand system-level impact in a quickly adapting, dynamic development environment.

Beyond pure performance modeling, you’ll keep a sharp eye on functional accuracy and QA, follow emerging academic and industry trends, and inject the relevant insights into the product.

You will also champion modern AI-assisted coding tools (e.g., Cursor AI, GitHub Copilot) to lift the productivity of the senior software engineers on your team and shorten iteration cycles.

Responsibilities

Lead and mentor a team of simulation and modeling engineers; set goals, review designs, and remove roadblocks. Design and implement transactional / cycle-accurate / bit-exact / event-driven models that faithfully represent advanced AI IP blocks (Transformers, CNN accelerators, custom DMA, interconnects, power-management units, etc.). Build automated flows to sweep architectural parameters and features, collect metrics, and visualize system-level impact on performance, area, power, and bandwidth. Analyze and debug complex issues such as deadlocks, race conditions, and performance hotspots; deliver concise root-cause reports and actionable recommendations. Collaborate daily with architecture, VLSI, compiler, and firmware teams to translate new algorithms and hardware ideas into model requirements and specifications. Own accuracy and QA of the simulation stack: golden-model alignment, coverage tracking, regression health, and release sign-off. Continuously survey academic papers and industry trends, extract meaningful insights, and propose innovative modeling techniques or architectural directions. Promote the adoption of AI-powered development tools to accelerate coding, code-review, documentation, and test generation across the team.

Requirements

• B.Sc./M.Sc. in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience developing performance/functional hardware models (System C, C++, Python, or similar).
• Proven track record with cycle-accurate or bit-exact frameworks and event-driven simulation—ability to balance fidelity vs. runtime.
• Knowledge of AI workloads (Transformers, CNNs) and experience profiling or optimizing them in PyTorch or equivalent frameworks.
• Demonstrated skill in system-level performance analysis: latency/bandwidth modeling, bottleneck identification, parameter sweeps.
• Extensive Experience in software quality: unit / integration testing, CI pipelines, coverage, and regression management.
• Passion for staying current with state-of-the-art AI tools and coding assistants; ability to introduce and champion them inside the team.
• Excellent communication skills and a collaborative mindset; comfortable interfacing with architects, RTL/VLSI, compiler, and firmware groups.
• Proven leadership experience: planning, prioritizing, and delivering complex software projects on time.
  
  

• Exposure to hardware verification (UVM, SystemVerilog) or emulator/FPGA prototyping environments.
• Familiarity with graph compilers, accelerator runtimes, or other AI-software stacks.
• Experience visualizing large performance datasets