Mixed signal verification- Graduate

We are seeking a graduate engineer to join the Retym mixed-signal verification team. The role involves verifying digital and analog designs using behavioral modeling, SystemVerilog, UVM, and Cadence Virtuoso. You will contribute to developing cutting-edge technology for the next generation of high-speed communication systems.

Requirements:

Minimum Qualifications

• Bachelor’s degree (or higher) in Electrical Engineering
• Exposure to digital design and verification using Verilog or SystemVerilog (through coursework, projects, or internships)
• Basic understanding of digital, analog and mixed-signal circuit concepts
• Familiarity with schematic design tools such as Cadence Virtuoso (academic) – advantage
  
  

• Familiarity with UVM (Universal Verification Methodology) concepts
• Exposure to both Synopsys and Cadence tool flows through university or internship projects
• Understanding of mixed-signal verification concepts, even if no direct industry experience
• Relevant universtiy courses:
• Advanced Design of Analog Circuits in Digital Processes
• Digital System Design and/or Digital logic systems
• Analog Electronics and/or Analog Integrated Circuits
  
  

• Collaborative Environment: Ability to work in a team and learn from senior engineers while contributing to verification of analog/mixed-signal designs.
• Communication: Clear written and verbal communication skills for documenting work, writing test plans, and presenting results. Demonstrated ability to ask questions, seek guidance, and share findings with multi-disciplinary teams.
• Self leaner, highly motivated.