Senior Physical Design Engineer

We are seeking an experienced Backend Design Engineer to join our growing team and contribute to cutting-edge semiconductor development. In this role, you will take ownership of complex backend design challenges, focusing on high-frequency, low-power designs and leading the full RTL-to-GDSII flow in advanced technology nodes. You will collaborate closely with internal teams and external vendors to deliver world-class silicon solutions.

Responsibilities

• Drive the complete RTL-to-GDSII backend design flow, from logic synthesis through tape-out.
• Define design constraints, integrate complex IPs, and manage automated block generators (e.g., memory compilers).
• Execute floorplanning, power grid (PG) mesh, placement and routing (P&R), and timing closure (STA).
• Implement low-power design methodologies, including definition, implementation, and verification.
• Perform IR-drop analysis, DFT integration, and design optimization for performance, power, and area.
• Collaborate with cross-functional teams and external vendors to ensure successful tape-outs.

Minimum Qualifications

• 10+ years of proven experience in backend design.
• Strong expertise across the full RTL-to-GDSII flow, including:
• Logic synthesis & equivalence checking
• Constraints definition and scripting
• IP integration and memory compilers
• Floorplanning, PG mesh, and P&R
• Low-power design methodologies
• Static timing analysis (STA) and IR-drop
• DFT integration
• BS/MS in Electrical or Computer Engineering from a leading university.

Preferred Qualifications

• Strong team player with excellent communication skills.
• Highly motivated, fast learner, and proactive problem-solver.
• Hands-on experience with Synopsys and Cadence toolsets.
• Familiarity with advanced techniques such as low-power flows, clock-mesh, multi-source CTS, and hierarchical design.
• Proven experience with tape-out procedures.
• Ability to read and understand RTL code.